How to trace module inputs and outputs?

I want to export my pytorch model (similar to yolo) for our own FPGA accelerator. I understand how to get out the modules (eg. weights/biases of convolutional modules etc.). What I do not know is how to trace inputs and outputs.
The model is not ‘linear’, there are some residual connections. Is there any standard way how this can be described?

I’d like to get a graph depicting that eg. output from first layer is used by the layer two and five…