Request for Support in Integrating the RISC-V Vector ISA Extension

1

Hello everyone,

We are a small team from the Institute of Software, Chinese Academy of Sciences, attempt to improve PyTorch support on RISC-V.

I would like to draw your attention to my previously submitted PR (#135570), which aims to add support for the RISC-V Vector ISA (RVV) extension to PyTorch. This feature can significantly improve the performance of running models on RISC-V architecture, but it has not received enough response to date.

We have already made preliminary optimization attempts in PR (#127867), especially for the DepthwiseConvKernel, and initial results have shown a threefold performance improvement, proving the potential of RVV.

Currently, this PR has not received enough feedback and discussion. I am very eager to hear opinions and suggestions from the community. Please help to promote this feature or provide advice that can help me move forward further. If you are interested in discussing in depth or participating, you can find relevant information in the PR mentioned above.

Looking forward to your feedback!

2

I don’t think that’s the case as the discussion is focused on enabling proper CI testing and is still ongoing. I’m sure malfet will follow up once he finds the time.

3

Understood, it’s great to hear that the conversation is still active and moving forward. I appreciate the importance of thorough CI testing, and thanks for keeping me in the loop.